Conventional optical projection lithography has been the standard silicon patterning technology for the past 20 years. It is an economical process due to its inherently high throughput, thereby providing a desirable low cost per part or die produced. A considerable infrastructure (including steppers, photomasks, resists, metrology, etc.) has been built up around this technology.
In this process, a mask, or “reticle”, includes a semiconductor circuit layout pattern typically formed of opaque chrome, on a transparent glass (typically SiO2) substrate. A stepper includes a light source and optics/lenses that project light coming through the reticle and images the circuit pattern, typically with a 4× to 5× reduction factor, on a photoresist film formed on a silicon wafer. The term “chrome” refers to an opaque masking material that is typically but not always comprised of chrome. The transmission of the opaque material may also vary such as in the case of an attenuating phase shift mask.
In a manufacturing process using a lithographic projection apparatus, a mask can be imaged onto a substrate that is at least partially covered by a layer of resist. Prior to this imaging step, the substrate may undergo various procedures, such as, priming, resist coating, and a soft bake. After exposure, the substrate can be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake, and a measurement/inspection of the imaged features. This array of procedures can be used as a basis to pattern an individual layer of a device, such as an IC. Such a patterned layer may then undergo various processes, such as etching, ion-implantation, doping, metallization, oxidation, chemical mechanical polishing (CMP), etc., all intended to complete an individual layer. If several layers are required, then part of all of the procedure, or a variant thereof, may need to be repeated for each new layer. Eventually, multiple devices can be present on the substrate. These devices can then be separated from one another by a technique such as dicing or sawing. Thereafter, the individual devices can be mounted on a carrier, connected to pins, etc.
The photolithography masks referred to above comprise geometric designs, also called mask features, corresponding to the circuit components or structures to be integrated onto a substrate. Layouts used to create such masks are typically generated using computer-aided design (CAD) programs, sometimes called electronic design automation (EDA). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. Design rules can define the space tolerance between circuit devices, such as, for example, gates, contact holes, or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way.
One of the goals in IC fabrication is to faithfully reproduce the original circuit design or layout on the wafer using the mask. Another goal is to use as much of the wafer real estate as possible. As the size of an IC is reduced and its density increases, however, the critical dimension (CD) of its corresponding mask approaches the resolution limit of the optical exposure tool. The resolution for an exposure tool can be defined as the minimum feature sizes that the exposure tool can repeatedly expose on the wafer. The resolution value of present exposure tools often constrains the CD for many advanced IC designs.
As the semiconductor industry continues to evolve, feature sizes of the pattern are driven to smaller resolution. To meet this demand, Resolution-Enhanced optical lithography Technologies (“RET”) have become popular as techniques for providing patterns with sub-wavelength resolution. These methods include off-axis illumination (“OAI”), optical proximity correction (“OPC”), and phase-shift masks (“PSMs”) also called alternating phase-shift masks (“altPSMs”). Such resolution-enhanced optical lithography methods are especially useful for generating physical devices on a wafer that require small size and tight design tolerance. Examples of such physical devices are the gate length of a transistor or the dimensions of contact cuts formed in interlayer dielectrics.
One of the most common commercial implementations of phase shift mask technology is the double exposure method. A first mask, often called a binary mask, contains most of the features at the gate level. The binary mask can be printed using standard lithography techniques. A second mask, often called an alternating phase-shift mask (altPSM) includes the critical, or small sized features at the gate level.
An example of a double exposure phase shift method is illustrated in FIGS. 1A and 1B. FIG. 1A shows a layout of the mask features including the binary gate mask and phase shift features needed for each phase shift printed transistor. FIG. 1A shows a layout 100 of the overlay of a binary photomask and an altPSM over active areas 102. The binary photomask includes a series of binary gate layouts 112. The altPSM includes the phase shifters (also called shifters) 122a and 122b, where phase shifters 122a have a 0° phase shift and phase shifters 122b have a 180° phase shift. In use, a photoresist is applied to a wafer and the wafer is exposed to both masks in succession followed by photoresist development. The final transistors 132 and 134 formed using the two masks shown in FIG. 1A are shown in FIG. 1B.
In some cases, the active region can assume a shape other than rectangular. For example, FIG. 2 shows a diagram 200 of an exemplary active region 202 having an L-shape. Other exemplary active regions can include notched shaped regions. Problems arise, however, when designing using a1tPSM with active regions that are shaped other than a plain rectangle. One particular problem is that gate lines 212 formed over a portion of the L-shaped active region 202 have rounded ends 214, as seen in FIG. 2. Moreover, the gate lines 212 are often formed with ends 214 not extending the entire length of the active region. Among other problems, these issues can result in significant transistor leakage.
Accordingly, the present invention solves these and other problems of the prior art to provide a method that forms semiconductor devices that have gate lines with squared ends. Moreover, the present invention allows for gate lines that extend beyond the active region so as to minimize transistor leakage.